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| (R) EL7154 Data Sheet March 8, 2007 FN7278.2 High Speed, Monolithic Pin Driver The EL7154 three-state pin driver is particularly well suited for ATE and level shifting applications. The 4A peak drive capability, makes the EL7154 an excellent choice when driving high speed capacitive lines. The P-Channel MOSFET is completely isolated from the power supply, providing a high degree of flexibility. Pin (7) can be grounded, and the output can be taken from pin (8) when a "source follower" output is desired. The N-Channel MOSFET has an isolated drain, but shares a common bus with pre-drivers and level shifter circuits. This is necessary to ensure that the N-Channel device can turn off effectively when VL goes below GND. In some power-FET and IGBT applications, negative drive is desirable to insure effective turn-off. The EL7154 can be used in these applications by returning VL to a moderate negative potential. Features * Comparatively low cost * Three-State output * 3V and 5V Input compatible * Clocking speeds up to 10MHz * 20ns Switching/delay time * 4A Peak drive * Isolated drains * Low output impedance: 2.5 * Low quiescent current: 5mA * Wide operating voltage: 4.5V to16V * Isolated P-Channel device * Separate ground and VL pins Pinout EL7154 (8 LD PDIP, 8 LD SOIC) TOP VIEW * Pb-free plus anneal available (RoHS compliant) Applications * Loaded circuit board testers * Digital testers * Level shifting below GND * IGBT drivers VDD 1 VH 8 THREE-STATE 2 LEVEL SHIFT AND LOGIC POUT 7 VL 6 INPUT NOUT * CCD drivers 3 4 GND VL 5 VL Truth Table THREE-STATE 0 0 1 1 INPUT 0 1 0 1 POUT Open Open HIGH Open NOUT Open Open Open LOW Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047, #5,352,578, #5,352,389, #5,351,012, #5,374,898 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1996, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL7154 Ordering Information PART NUMBER EL7154CN EL7154CNZ EL7154CS EL7154CS-T7 EL7154CS-T13 EL7154CSZ (See Note) EL7154CSZ-T7 (See Note) EL7154CSZ-T13 (See Note) PART MARKING EL7154CN EL7154CN Z 7154CS 7154CS 7154CS 7154CSZ 7154CSZ 7154CSZ TAPE AND REEL 7" 13" 7" 13" PACKAGE 8 Ld PDIP 8 Ld PDIP* (Pb-free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 PKG. DWG. # *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Nominal Operating Voltage Range PIN VL VDD to VL VH to VL VDD to VH VDD MIN -3 5 2 -0.5 5 MAX 0 15 15 15 15 2 FN7278.2 March 8, 2007 EL7154 Absolute Maximum Ratings (TA = +25C) Supply (VDD to VL; VH to VL, VH to GND), V+ to VH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V Input Pins . . . . . . . . . . . . . . . . . -0.3V below VL to +0.3V above VDD Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4A Thermal Information Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Power Dissipation SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER INPUT VIH IIH VIL IIL VHVS OUTPUT ROH ROL IOUT IPK IDC POWER SUPPLY IS VS IG IH TA = +25C, VDD = +12V, VH = +12V, VL = -3V, unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS Logic "1" Input Voltage Logic "1" Input Current Logic "0" Input Voltage Logic "0" Input Current Input Hysteresis VIL = 0V VIH = VDD 2.4 0.1 10 0.6 0.1 0.3 10 V A V A V Pull-Up Resistance Pull-Down Resistance Output Leakage Current Peak Output Current Continuous Output Current IOUT = -100mA IOUT = +100mA VDD/GND Source/Sink Source/Sink 200 1.5 2 0.2 4.0 4 4 10 A A mA Power Supply Current Operating Voltage Current to GND (Pin 4) Off Leakage at VH Inputs = VDD 4.5 1 2.5 16 mA V A A 1 Pin 8 = 0V 1 10 10 AC Electrical Specifications PARAMETER TA = +25C unless otherwise specified DESCRIPTION TEST CONDITIONS MIN TYP MAX UNITS SWITCHING CHARACTERISTICS (VDD = VH = 12V; VL = -3V) tR tF tD-1 tD-2 tD-1 tD-2 Rise Time CL = 100pF CL = 2000pF Fall Time CL = 100pF CL = 2000pF Turn-Off Delay Time Turn-On Delay Time Three-State Delay Three-State Delay CL = 2000pF CL = 2000pF 4 20 4 20 20 10 25 25 25 25 ns ns ns ns 25 ns 25 ns 3 FN7278.2 March 8, 2007 EL7154 Timing Table Standard Test Configuration 4 FN7278.2 March 8, 2007 EL7154 Typical Performance Curves FIGURE 1. MAX POWER DERATING CURVES FIGURE 2. SWITCH THRESHOLD vs SUPPLY VOLTAGE FIGURE 3. INPUT CURRENT vs VOLTAGE FIGURE 4. PEAK DRIVE vs SUPPLY VOLTAGE FIGURE 5. QUIESCENT SUPPLY CURRENT FIGURE 6. "ON" RESISTANCE vs SUPPLY VOLTAGE FIGURE 7. AVERAGE SUPPLY CURRENT vs VOLTAGE AND FREQUENCY FIGURE 8. RISE/FALL TIME vs LOAD 5 FN7278.2 March 8, 2007 EL7154 Typical Applications FIGURE 9. PIN DRIVER FIGURE 10. ADJUSTABLE AMPLITUDE PULSE GENERATOR FIGURE 11. IGBT DRIVER WITH NEGATIVE SWING FIGURE 12. PMDS FOLLOWER FIGURE 13. RESONANT GATE DRIVER 6 FN7278.2 March 8, 2007 EL7154 Small Outline Package Family (SO) A D N (N/2)+1 h X 45 A E E1 PIN #1 I.D. MARK c SEE DETAIL "X" 1 B (N/2) L1 0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X SEATING PLANE L 4 4 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07 7 FN7278.2 March 8, 2007 EL7154 Plastic Dual-In-Line Packages (PDIP) D E N PIN #1 INDEX SEATING PLANE L e b A2 A c E1 A1 NOTE 5 eA eB 1 2 b2 N/2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. C 2/07 2 1 NOTES All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN7278.2 March 8, 2007 |
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